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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adg733/adg734 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s. a. tel : 781/32 9 -4700 www.ana log.com fax: 78 1 /3 2 6 -8 7 0 3 ? analog devices, inc., 2014 cmos, 2.5 low voltage, t riple/quad spdt switches features 1.8 v to 5.5 v single supply 2.5 v dual supply 2.5 on resistance 0.5 on resistance flatness 100 pa leakage currents 19 ns switching times triple spdt: adg733 quad spdt: adg734 small tssop and qsop packages low power consumption ttl/cmos compatible inputs applications data acquisition systems communication systems relay replacement audio and video switching battery powered systems general description the adg733 and adg734 are low voltage, cmos devices comprising three independently selectable spdt (single pole, double throw) switches and four independently selectable spdt switches respectively. low power consumption and operating supply range of 1.8 v to 5.5 v and dual 2.5 v make the adg733 and adg734 ideal for battery powered, portable instruments. all channels exhibit bre ak-before-make switching action preventing momentary shorting when switching channels. an en input on the adg733 is used to enable or disable the device. when disabled, all chan nels are switched off. these 2? multiplexers/spdt switches are designed on an enhanced submicron process that provides low power dissipation yet gives high switching speed, very low on resistance, high signal bandwidths, and low leakage currents. on resistance is in the region of a few ohms, is closely matched between switches, and is very flat over the full signal range. these parts can operate equally well in either direction and have an input signal range that ex tends to the supplies. the adg733 is available in small tssop and qsop packages, while the adg734 is available in a small tssop package. product highlights 1. single/dual supply operation. the adg733 and adg734 are fully specified and guaranteed with 3 v and 5 v single supply rails and 2.5 v dual supply rails. 2. low on resistance (2.5 ? typical) 3. low power consumption (<0.01 w) 4. guaranteed break-before-make switching action functional block diagrams s1b d1 s1a a0 s2a d2 s2b s3b d3 s3a a1 adg733 switches shown for a ??input logic s1a d1 s1b in1 in2 s2b d2 s2a s3a d3 s3b in3 in4 s4b d2 s4a adg734 en a2 logic
rev. b ? adg733/adg734?pecifications 1 b version ?0 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 2.5 ? typ v s = 0 v to v dd , i ds = 10 ma; 4.5 5.0 ? max test circuit 1 on resistance match between 0.1 ? typ v s = 0 v to v dd , i ds = 10 ma channels ( ? r on ) 0.4 ? max on resistance flatness (r flat(on) ) 0.5 ? typ v s = 0 v to v dd , i ds = 10 ma 1.2 ? max leakage currents v dd = 5.5 v source off leakage i s (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; 0.1 0.3 na max test circuit 2 channel on leakage i d , i s ( on) 0.01 na typ v d = v s = 1 v, or 4.5 v; 0.1 0.5 na max test circuit 3 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 4 pf typ dynamic characteristics 2 t on 19 ns typ r l = 300 ? , c l = 35 pf; 34 ns max v s = 3 v, test circuit 4 t off 7 ns typ r l = 300 ? , c l = 35 pf; 12 ns max v s = 3 v, test circuit 4 adg733 t on ( en )2 0 ns typ r l = 300 ? , c l = 35 pf; 40 ns max v s = 3 v, test circuit 5 t off ( en )7 ns typ r l = 300 ? , c l = 35 pf; 12 ns max v s = 3 v, test circuit 5 break-before-make time delay, t d 13 ns typ r l = 300 ? , c l = 35 pf; 1 ns min v s = 3 v, test circuit 6 charge injection 3pc typ v s = 2 v, r s = 0 ? , c l = 1 nf; test circuit 7 off isolation ?2 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 channel-to-channel crosstalk ?7 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 9 ? db bandwidth 160 mhz typ r l = 50 ? , c l = 5 pf, test circuit 10 c s (off) 11 pf typ f = 1 mhz c d , c s ( on) 34 pf typ f = 1 mhz power requirements v dd = 5.5 v i dd 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max notes 1 temperature range is as follows: b version: ?0 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = 5 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted.)
rev. b ? adg733/adg734 b version ?0 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on )6 ? typ v s = 0 v to v dd , i ds = 10 ma; 11 12 ? max test circuit 1 on resistance match between 0.1 ? typ v s = 0 v to v dd , i ds = 10 ma channels ( ? r on ) 0.4 ? max on resistance flatness (r flat(on) )3 ? typ v s = 0 v to v dd , i ds = 10 ma leakage currents v dd = 3.3 v source off leakage i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v; 0.1 0.3 na max test circuit 2 channel on leakage i d , i s ( on) 0.01 na typ v s = v d = 1 v or 3 v; 0.1 0.5 na max test circuit 3 digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 4 pf typ dynamic characteristics 2 t on 28 ns typ r l = 300 ? , c l = 35 pf; 55 ns max v s = 2 v, test circuit 4 t off 9 ns typ r l = 300 ? , c l = 35 pf; 16 ns max v s = 2 v, test circuit 4 adg733 t on ( en )2 9 ns typ r l = 300 ? , c l = 35 pf; 60 ns max v s = 2 v, test circuit 5 t off ( en )9 ns typ r l = 300 ? , c l = 35 pf; 16 ns max v s = 2 v, test circuit 5 break-before-make time delay, t d 22 ns typ r l = 300 ? , c l = 35 pf; 1 ns min v s = 2 v, test circuit 6 charge injection 3pc typ v s = 1 v, r s = 0 ? , c l = 1 nf; test circuit 7 off isolation ?2 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 channel-to-channel crosstalk ?7 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 9 ? db bandwidth 160 mhz typ r l = 50 ? , c l = 5 pf, test circuit 10 c s (off) 11 pf typ f = 1 mhz c d , c s ( on) 34 pf typ f = 1 mhz power requirements v dd = 3.3 v i dd 0.001 a typ digital inputs = 0 v or 3.3 v 1.0 a max notes 1 temperature ranges are as follows: b version: ?0 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = 3 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted.) specifications 1
rev. b ? adg733/adg734?pecifications 1 dual supply b version ?0 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance (r on ) 2.5 ? typ v s = v ss to v dd , i ds = 10 ma; 4.5 5.0 ? max test circuit 1 on resistance match between 0.1 ? typ v s = v ss to v dd , i ds = 10 ma channels ( ? r on ) 0.4 ? max on resistance flatness (r flat(on) ) 0.5 ? typ v s = v ss to v dd , i ds = 10 ma 1.2 ? max leakage currents v dd = +2.75 v, v ss = ?.75 v source off leakage i s (off) 0.01 na typ v s = +2.25 v/?.25 v, v d = ?.25 v/+2.25 v; 0.1 0.3 na max test circuit 2 channel on leakage i d , i s ( on) 0.01 na typ v s = v d = +2.25 v/?.25 v, test circuit 3 0.1 0.5 na max digital inputs input high voltage, v inh 1.7 v min input low voltage, v inl 0.7 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 4 pf typ dynamic characteristics 2 t on 21 ns typ r l = 300 ? , c l = 35 pf; 35 ns max v s = 1.5 v, test circuit 4 t off 10 ns typ r l = 300 ? , c l = 35 pf; 16 ns max v s = 1.5 v, test circuit 4 adg733 t on ( en )2 1 ns typ r l = 300 ? , c l = 35 pf; 40 ns max v s = 1.5 v, test circuit 5 t off ( en )1 0 ns typ r l = 300 ? , c l = 35 pf; 16 ns max v s = 1.5 v, test circuit 5 break-before-make time delay, t d 13 ns typ r l = 300 ? , c l = 35 pf; 1 ns min v s = 1.5 v, test circuit 6 charge injection 5pc typ v s = 0 v, r s = 0 ? , c l = 1 nf; test circuit 7 off isolation ?2 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 channel-to-channel crosstalk ?7 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 9 ? db bandwidth 200 mhz typ r l = 50 ? , c l = 5 pf, test circuit 10 c s (off) 11 pf typ f = 1 mhz c d , c s ( on) 34 pf typ f = 1 mhz power requirements v dd = 2.75 v i dd 0.001 a typ digital inputs = 0 v or 2.75 v 1.0 a max i ss 0.001 a typ v ss = ?.75 v 1.0 a max digital inputs = 0 v or 2.75 v notes 1 temperature range is as follows: b version: ?0 c to +85 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = +2.5 v 10%, v ss = ?.5 v 10%, gnd = 0 v, unless otherwise noted.)
rev. b adg733/adg734 ? absolute maximum ratings 1 (t a = 25 c, unless otherwise noted.) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ?.5 v analog inputs 2 . . . . . . . . . . . . . . v ss ?0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 2 . . . . . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma (pulsed at 1 ms, 10% duty cycle max) continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 30 ma operating temperature range industrial (a, b versions) . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c 16-lead tssop, ja thermal impedance . . . . . . . 150.4 c/w 20-lead tssop, ja thermal impedance . . . . . . . . . 143 c/w 16-lead qsop, ja thermal impedance . . . . . . . 149.97 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . . . 300 c ir reflow, peak temperature (<20 sec) . . . . . . . . . . . . 235 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at a, en, in, s, or d will be clamped by internal diodes. current should be limited to the maximum ratings given. pin configurations 10 9 13 12 11 15 14 16 8 1 2 3 4 7 6 5 top view (not to scale) adg733 s2b s1b d1 d2 v dd s2a s3b d3 a1 a0 s1a s3a en v ss gnd a2 14 13 12 11 17 16 15 19 18 20 10 9 8 1 2 3 4 7 6 5 top view (not to scale) adg734 nc = no connect in1 s4b d4 s4a in4 s1a d1 s1b s3b nc v dd v ss gnd s2b d2 s2a in2 in3 s3a d3 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg733/adg734 feature proprietary esd protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. tssop/qsop tssop
rev. b adg733/adg734 ? table i. adg733 truth table a2 a1 a0 en on switch xxx1 none 0000d 1-s1a, d2-s2a, d3-s3a 0010d 1-s1b, d2-s2a, d3-s3a 0100d 1-s1a, d2-s2b, d3-s3a 0110d 1-s1b, d2-s2b, d3-s3a 1000d 1-s1a, d2-s2a, d3-s3b 1010d 1-s1b, d2-s2a, d3-s3b 1100d 1-s1a, d2-s2b, d3-s3b 1110d 1-s1b, d2-s2b, d3-s3b x = don? care. table ii. adg734 truth table logic switch a switch b 0 off on 1o n off terminology v dd most positive power supply potential v ss most negative power supply in a dual supply application. in single supply applications, this should be tied to ground close to the device. i dd positive supply current i ss negative supply current gnd ground (0 v) reference s source terminal. may be an input or output. dd rain terminal. may be an input or output. a x logic control input en active low device enable v d (v s )a nalog voltage on terminals d and s r on ohmic resistance between d and s ? r on on resistance match between any two channels (i.e., r on max and r on min) r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. i s (off) source leakage current with the switch ?ff i d , i s (on) channel leakage current with the switch ?n v inl maximum input voltage for logic ? v inh minimum input voltage for logic ? i inl (i inh ) input current of the digital input c s (off) ?ff?switch source capacitance. measured with reference to ground. c d , c s (on) ?n?switch capacitance. measured with reference to ground. c in digital input capacitance t on delay time measured between the 50% and 90% points of the digital inputs and the switch ?n?condition t off delay time measured between the 50% and 90% points of the digital input and the switch ?ff?condition t on ( en )d elay time between the 50% and 90% points of the en digital input and the switch ?n?condition t off ( en )d elay time between the 50% and 90% points of the en digital input and the switch ?ff?condition t open ?ff?time measured between the 80% points of both switches when switching from one address state to another charge a measure of the glitch impulse transferred injection from the digital input to the analog output during sw itching off isolation a measure of unwanted signal coupling through an ?ff?switch. crosstalk a me asure of unwanted signal that is coupled through from one channel to another as a result of para- sitic c apacitance on response the frequency response of the ?n?switch insertion loss the loss due to the on resistance of the switch
rev. b ? t ypical performance characteristicsadg733/adg734 v d , v s , drain or source voltage ?v 8 01234 7 6 5 4 3 2 1 0 on resistance ? t a = 25c v ss = 0v v dd = 4.5v v dd = 5.5v v dd = 3.3v v dd = 2.7v 5 tpc 1. on resistance as a function of v d (v s ) for single supply v d or v s ?drain or source voltage ?v 0 0.5 7 6 5 4 3 2 1 0 on resistance ? 1.0 1.5 2.0 2.5 3.0 8 +25c ?0c +85c v dd = 3v v ss = 0v tpc 4. on resistance as a function of v d (v s ) for different temperatures, single supply v s , (v d = v dd ? v s ) ?v 0.10 0 0.5 current ?na v dd = 3v v ss = gnd t a = 25c i s , i d (on) i s (off) 0.08 0.06 0.04 0.02 0 ?.02 ?.04 ?.06 ?.08 ?.10 1.0 1.5 2.0 2.5 3.0 tpc 7. leakage currents as a function of v d (v s ) v d , v s , drain or source voltage ?v 8 ? ? ? 0 2 7 6 5 4 3 2 1 0 on resistance ? t a = 25 c v dd = +2.5v v ss = ?.5v 3 1 tpc 2. on resistance as a function of v d (v s ) for dual supply v d , v s , drain or source voltage ?v 8 ? ? ? 0 2 7 6 5 4 3 2 1 0 on resistance ? v dd = +2.5v v ss = ?.5v 3 ?0 c 1 +85 c +25 c tpc 5. on resistance as a function of v d (v s ) for different temperatures, dual supply v s , (v d = v dd ? s ) ?v 0.15 ? ? current ?na v dd = +2.5v v ss = ?.5v t a = 25 c i s (off) 0.10 0.05 0 ?.05 ?.10 ?.15 ? 0123 i s , i d (on), v d = v s tpc 8. leakage currents as a function of v d (v s ) v d , or v s drain or source voltage ?v 8 02 7 6 5 4 3 2 1 0 on resistance ? v dd = 5v v ss = 0v 3 ?0c 1 +85c +25c 45 tpc 3. on resistance as a function of v d (v s ) for different temperatures, single supply v s , (v d = v dd ? v s ) ?v 0.1 0123 5 current ?na v dd = 5v v ss = gnd t a = 25c 4 i s , i d (on) i s (off) 0.05 0 ?.05 ?.1 ?.15 tpc 6. leakage currents as a function of v d (v s ) temperature ?c 0.25 5 current ?na v dd = +2.5v v ss = ?.5v v d = +2.25v/?.25v v s = ?.25v/+2.25v v dd = 5v v ss = gnd v d = 4.5v/1.0v v s = 1.0v/4.5v i s , i d (on) i s (off) 0.20 0.15 0.10 0.05 0 ?.05 20 35 50 65 80 ?.10 tpc 9. leakage currents as a function of temperature
rev. b adg733/adg734 ? temperature ? c 0.25 5 current ?na v dd = 3v v ss = gnd v d = 2.7v/1v v s = 1v/2.7v i s , i d (on) i s (off) 0.20 0.15 0.10 0.05 0 ?.05 20 35 50 65 80 ?.10 tpc 10. leakage currents as a function of temperature v ss = 3v v dd = gnd v dd = +2.5v v ss = ?.5v v dd = 5v v ss = gnd t a = 25c frequency ?khz 10m 0.1 current ?a 1m 100 10 1 100n 10n 110 100 1000 10000 tpc 13. input current, i dd vs. switching frequency voltage ?v ? ? 20 10 0 ?0 q inj ?pc ? 0 1 2 3 30 t a = 25 c v dd = 5v v ss = gnd v dd = +2.5v v ss = ?.5v v dd = 3v v ss = gnd 45 tpc 16. charge injection vs. source voltage temperature ?c 40 ?0 time ?ns 35 30 25 20 15 10 020406080 0 v ss = gnd t on , v dd = 3v t off , v dd = 3v t on , v dd = 5v t off , v dd = 5v 5 tpc 11. t on /t off times vs. temperature frequency ?khz 0 30k attenuation ?db ?0 ?0 ?0 ?0 ?00 ?20 100k 1m 10m 100m v dd = 5v t a = 25 c tpc 14. off isolation vs. frequency frequency h z 0 10m 10k ? ? 100k 1m 100m ? on response db ? ?0 ?2 ?4 ?6 v dd = 5v t a = 25 c tpc 12. on response vs. frequency frequency ?khz 0 30k attenuation ?db ?0 ?0 ?0 ?0 ?00 ?20 100k 1m 10m 100m v dd = 5v t a = 25 c tpc 15. crosstalk vs. frequency
rev. b adg733/adg734 ? i ds v1 sd v s r on = v1/i ds test circuit 1. on resistance t est circuits v d i s (off) sd v s a test circuit 2. i s (off) i d (on) sd a v d nc test circuit 3. i d (on) s1a d1 vs1b in/en gnd r l 300 c l 35pf v out v dd v dd 0.1f s1b vs1a v ss v ss 0.1f t on 90% 90% 50% 50% address drive v out vs1b vs1a t off test circuit 4. switching times, t on , t off 3v 50% output 50% t on (en) 0.9v 0 0v 0v enable drive (v in ) 0.9v 0 v o t off ( en) a2 v o d1 v s a1 a0 en gnd adg733 s1a s1b v in 50 r l 300 c l 35pf v dd v ss v ss v dd 0.1f test circuit 5. enable delay, t on ( en ), t off ( en ) v out d1 v s gnd adg733/ adg734 sa sb v in 50 address* *a0, a1, a2 for adg733, in1-4 for adg734 v ss 0.1f v ss v dd v dd 0.1f r l 300 c l 35pf address 3v v out t open 80% 80% 0v v s test circuit 6. break-before-make delay, t open
rev. b adg733/adg734 ?0 * in1? for adg734 gnd v dd adg733/ adg734 v out c l 1nf v s r s d s v dd v ss v ss v in en * v out 3v v out logic input (v in ) q inj = c l v out 0v test circuit 7. charge injection v s v out 50 network analyzer r l 50 in gnd v in s d 50 off isolation = 20 log v out v s v dd 0.1 f v dd v ss 0.1 f v ss test circuit 8. off isolation channel-to-channel crosstalk = 20 log gnd v dd 0.1f v dd v ss 0.1f v ss sa d sb v s v out network analyzer r l 50 in v out v s 50 r 50 test circuit 9. channel-to-channel crosstalk v s v out 50 network analyzer r l 50 in gnd v in s d insertion loss = 20 log v out with switch v out without switch v dd 0.1f v dd v ss 0.1f v ss test circuit 10. bandwidth
data sheet adg733/adg734 outline dimensions fig ure 11. 16-lead shrink small outline package [qsop] (rq-16) dimensions shown in inches and (millimeters) fig ure 12. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters compliant to jedec standards mo-137-ab controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 16 9 8 1 seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.041 (1.04) ref 0.010 (0.25) 0.006 (0.15) 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 8 0 coplanarity 0.004 (0.10) 0.065 (1.65) 0.049 (1.25) 0.069 (1.75) 0.053 (1.35) 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 01-28-2008-a 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.7 5 0.60 0.4 5 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab --11-- rev. b
adg733/adg734 data sheet fig ure 13. 20-lead thin shrink small outline package [tssop] (ru-20) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adg733brqz ?40c to +85c 16-lead shrink small outline package [qsop] rq-16 adg733brqz-reel ?40c to +85c 16-lead sh rink small outline package [qsop] rq-16 adg733bru-reel7 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 adg733bruz ?40c to +85c 16-lead thin sh rink small outline package [tssop] ru-16 adg733bruz-reel ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 adg733bruz-reel7 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 adg734bru ?40c to +85c 20-lead thin sh rink small outline package [tssop] ru-20 adg734bru-reel ?40c to +85c 20-lead thin shrink small outline package [tssop] ru-20 adg734bruz ?40c to +85c 20-lead thin sh rink small outline package [tssop] ru-20 adg734bruz-reel ?40c to +85c 20-lead thin shrink small outline package [tssop] ru-20 adg734bruz-reel7 ?40c to +85c 20-lead thin shrink small outline package [tssop] ru-20 1 z = rohs compliant part. revision history 4/14rev. a to rev. b updated outline dimensions ....................................................... 11 changes to ordering guide .......................................................... 12 11/02data sheet changed from rev. 0 to rev. a. changes to features ................................................................... 1 changes to product highlights ........................................ 1 changes to specifications ...................................................... 2 changes to absolute maximum ratings note 2 ........... 5 changes to terminology table ............................................... 6 replaced tpcs 2, 5, 8, and 9 ........................................................... 7 edits to tpcs 6 and 7 ....................................................................... 7 replaced tpc 12............................................................................... 8 edits to tpcs 13 and 16 ................................................................... 8 replaced test circuits 8 and 9 ...................................................... 10 added test circuit 10 .................................................................... 10 updated outline dimensions ............................................ 11 compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarit y 0.10 ?2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d01602-0-4/14(b) --12-- rev. b

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